在下面的示例中，cpuid指令采用%eax寄存器中的输入，然后在四个寄存器中给出输出：% eax、%ebx、%ecx、%edx。
In the following example, the cpuid instruction takes the input in the % eax register and gives output in four registers: % eax, % ebx, % ecx, % edx.
这样，这里的%eax既可以用作输入寄存器，又可以用作输出寄存器。
当主控门打开时，经过转换的输入信号脉冲通过它进入计数寄存器，并在此统计，然后通过显示电路输出。
While the main gate is open, the conditioned input signal pulses are passed through to the counting register, where they are tallied and then scaled for output by the display circuitry.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
研究了串行输入，并行输出单向移位寄存器的功能。
The function of the single-direction shift register which is serial input and parallel output is mainly studied.
利用一个片内控制寄存器，用户可以设置不同的工作条件，包括模拟输入范围和配置、输出编码、功耗管理及通道序列化。
An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
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