该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
这里CPLD主要实现逻辑控制部分的作用，主要完成了采样脉冲产生、地址译码等功能。
We use the CPLD to realize some control circuits, such as address decoder circuits and generate the sample impulses.
最小和算法具有简单、容易实现的特点，但使译码性能较大幅度地降低。
Minimum sum algorithm is very simple and is easy for hardware implementation. But the decoding performance is degraded.
其基本思想是CPU通过寄存器控制VCP，并由EDMA控制器同VCP进行数据交互来实现译码。
The basic idea is that CPU accesses VCP through registers, while exchanging data between VCP and EDMA controller to realize decoding.
应用锁相环集成电路ne567对音频信号的鉴相原理实现对控制信号的译码输出，控制井下仪器马达工作。
The latch phase circle circuit NE567 functions as phase demodulation of audio frequency signals for realizing decoding output of the control signals to control the downhole motor operations.
由于嵌入式系统硬件资源的有限性，本论文以解释方式为主全面的分析研究了数控系统中译码模块所要实现的绝大部分功能。
Mainly using interpretive mode, it rounded analysis and research majority function which need realized in decoding module, owing to finiteness of hardware resource in embedded system.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
最后，在综合了以上研究的基础上，实现了H。263视频编译码软件的实验系统。
At last, based on the integration of the upwards research, we realize the H. 263 video encoding and decoding software experiment system.
在相同条件下，最大后验概率译码算法比最大似然译码算法有更低误比特率，但由于计算量和复杂度过大而不适合硬件实现。
While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation.
本论文给出了一种简单分组码-（7，4）汉明码编、译码器的单片机实现方案。
This paper provides a hardware-realizing scheme of coding and decoding of(7,4) Hamming Code using the single chip microcomputer.
接着介绍了R S码的编码原理和时域迭代译码算法，在此基础上设计实现RS码编码器和译码器。
Then, the code theory and time-domain iterative decode algorithm of RS code is introduced, RS coder and decoder are designed and implemented in this base.
由于校验阵和生成阵满足一定的关系，因此可以采用修正的译码算法来实现对码字的不等错误保护。
Due to the particular relation of generator matrix and parity check matrix, it can achieve unequal error protection performance with the modified decoding algorithm.
首先介绍了H . 263建议中视频信号纠错编码的应用，然后着重介绍了BCH(511,493)纠错编译码的设计及其实现。
After a brief description of error correcting code of applied digital video signals in H. 263, this paper focuses on the design and implementation of BCH (511,493) error correcting code.
文章提出了一种新的基于VHDL语言的汉明码的编码和译码的实现方法。
The paper proposes a new method for Hanming encoder and Hanming decoder which is based on the VHDL language.
所实现的编译码器能对BCH(23,12)码进行正确地编码和译码，能纠正小于或等于3位的随机错误。
The encoder can correctly encode and decode the BCH (23, 12) code which can correct less than or equal to 3 bit error.
在此提出了一种幸存路径存储器的新实现方法，与传统的回溯法和寄存器法相比，该方法具有存储器用量少、译码延迟小的特点。
Compared to traditional register-exchange and trace-back methods, the main advantages of this method lie in less memory and little decoding delay.
指令译码器将编码指令信号进行译码，最后由驱动电路来驱动执行电路实现各种指令的操作。
Encoding instruction decoder for decoding command signals, and finally by the drive circuit to drive the implementation of circuit operation to achieve a variety of commands.
这些内容对于LDPC编译码的实现有一定的指导意义。
基于CPLD设计了一种能实现该种转换的HDB3码编译码器。
Based on the CPLD, a circuit of HDB3 CODEC is designed in this article to realize this transform.
说明：根据BCH码的编译码原理，用C语言实现的BCH码编译码过程，并进行误码率分析。
According to the principle of BCH code , the program will realize the encodeing and decoding of BCH code, the analysis of BER.
为了实现GMSK信号解调，接收机中dsp实现了调制信号的误差频谱估计、位同步恢复及译码。
To demodulate GMSK signal, DSP is used in receiver to achieve error spectrum estimation, bit synchronization recovery and decode.
由于其运算矩阵为稀疏矩阵，可用稀疏矩阵算法对译码进一步简化，使译码算法的集成电路实现容易。
Because the matrix is a sparse matrix, the decoding can be simplified and its implementation by VISL can become easy.
分析了HDB3译码器的原理，提出了一种基于FPGA技术的HDB3译码器的快速实现方法。
The principle of HDB3 decoder is analyzed. A quick way to implement HDB3 decoder based on FPGA is proposed.
随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。
With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.
为降低低密度奇偶检验码译码的硬件实现复杂度，提出了一种可变步长均匀量化“和积”译码算法。
A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.
利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。
According to the structure of Quasi-Cyclic LDPC code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
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