双稳态触发器电路一种触发器电路，有两种固定状态。
Bistable trigger circuit a trigger circuit that has two stable states.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
以555定时器构成的单稳态触发器这一典型电路为基础自制一种实用测试器，较详细的分析了该器件的工作原理、耦合方式、使用方法。
A tester is made based on the typical circuit of the monostable trigger made of 555 timers. It operation principle, coupling way and usage are analysed in great detail.
尽管期望这种集成电路作为一种锁存器电路，它也可以当作推荐的标准触发器。
Even though this IC (integrated circuit) is supposed to work as a latch circuit, it can also be made to function as RS (recommended standard) flip-flop.
改进后的触发器，具有保持、置0、置1、翻转四种功能，是一种很理想的电路。
The improved flip is an ideal circuit with the four function of presetting to 1, presetting to 0, maintaining, turning over.
尽管期望这种集成电路作为一种锁存器电路，它也可以当作推荐的标准触发器。
Even though this IC is supposed to work as a latch circuit, it can also be made to function as RS (recommended standard) flip-flop.
双稳态触发器是具有记忆功能的核心逻辑单元，在数字集成电路中发挥着重要作用。
Stable state trigger is core logical unit which has memory function and plays an important role in digital integrated circuit.
通过设计实例表明，基于触发器次态方程设计同步时序电路具有一定的优点和实用意义。
Some design examples show that the design of synchronous sequential circuits based on next state equations of flip-flops is of great advantage and practical significance.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit. Examples are also given.
该芯片的判决电路采用SCFL(源级耦合晶体管逻辑)的D触发器结构，根据矢量叠加原理设计，采用差动电流放大器构成可调移相器。
The decision circuit of the chip is applied with a DFF using SCFL structure and its tuned phase shifter with differential current amplifiers according to the principle of vector addition.
采用防抖动触发器和单稳电路防止抖动和重复动作。
The preventative dithering trigger and mono-stability circuit was adopted to prevent dithering and repeated actions.
通过对原有PFD电路结构进行重新设计，在传统D触发器PFD的基础上提出了两种新型PFD：传输门D触发器型PFD和基于锁存器的PFD。
Through redesigning the structure of the original PFD circuit and based on the traditional D trigger PFD, two new PFDs, transmission gate D trigger PFD and flip-latch based PFD were proposed.
应用传输函数理论对四值CMOS触发器进行了电路设计。
The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory.
应用CD4098单稳态触发器组成了三相过零触发电路，达到了较为理想的调功效果。
The three-phase zero-detection trigger made up of CD4098 single side stale trigger can produce ideal effect.
研制的触发系统可以同时触发两路开关，实现了触发系统的紧凑化，同时并能抑制栅极尖峰电压防止其返回触发器内部电路。
The trigger system can trigger two thyratron at the same time, achieved the compact of the trigger system, and it can avoid the grid spike come into the inner circuit of trigger system.
介绍了一种由80c196 KC单片机构成的三相全控桥式整流电路的数字触发器。
The paper describes a digital trigger for three-phase fully-controlled bridge, using a single chip microprocessor 80c196kc.
该文以双反相器闩锁电路为基本存贮单元，采用开关级设计方法设计出一种新型的CMOSJK触发器。
Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level.
阈值检测器就是一种回差范围较大的锁存电路，与施密特触发器相似。
The threshold detector is similar to a Schmitt Trigger in that it is a latch circuit with a large dead zone.
该方法之关键在于直接从时序电路的状态转换图（STD）获得J-K、D和T触发器的激励方程式。
The crux of this method is that excitation equations for J K, D and T flip flops are obtained directly from the state transition diagrams(STDs).
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
该分频器采用源极耦合场效应管逻辑电路，基本结构与T触发器相同。
The divider is designed in the Source Coupled Logic, with the structure being similar to the t filp flop.
该电路利用接近开关作为控制集成触发器的触发。
This circuit makes use of near-switch and controls integrated trigger triggering.
特别是多阈值时钟竞争型触发器，不仅可以降低电路的漏电流功耗，还能降低电路的时钟网络的功耗。
Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.
图1为本发明所述高压纳灯的新型电路的一种，图中灯泡1、镇流器2、触发器3、特殊滤波电抗器4、电容器5。
Image 1 of this invention describes one kind of new circuit for HPS lamps, in the image: lamp 1, ballast 2, trigger 3, a special filter reactor 4, and capacitor 5.
作为常规ECL门的补充类型，常可用于简化一般ECL电路结构，例如ECL双边沿D触发器。
The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.
在数字电路中，数字频率计属于时序电路，它主要由具有记忆功能的触发器构成。
In the digital circuit, the digital frequency meter belongs to the sequence circuit, it mainly by has the memory function trigger constitution.
交替互补定位器由D型触发器和通用门电路构成，它被证明为是一个完全故障定位的定位器。
The alternating-complementary locator is constructed by D-flip-flops and gate circuits. It is proved that it is totally fault locating.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit.
应用推荐