在我了解中常见的有3种主控解码芯片的方案。
I have a common understanding of three kinds of program control decoder chip.
系统是要完成一个语音解码芯片的专用集成电路的设计。
本文简要介绍应用前景广阔的MPEG - 2视频解码芯片的新进展。
A brief survey is given to the new advances of MPEG-2 video decoder chips.
第三章具体描述应用于HD TV信源解码芯片的实时操作系统存储管理策略的设计及实现。
Chapter 3 presents the design and implementation of memory management of RTOS for the HDTV integrated source decoder chip.
视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。
The architecture of video decoder is transforming from dedicated hardware to HW/SW partition owing to the powerful process of hardware and the flexibility and programmability of software.
在分析IIC总线协议的基础上，文中详细叙述了DM 642通过IIC模块对视频编解码芯片的寄存器进行配置、校验的流程。
IIC bus protocol analysis on the basis of a detailed description in the text adopted by the IIC module DM642 video decoder chip register configuration, calibration process.
鉴于此，本文基于电子科技大学VLSI实验室的某超大规模数字解码芯片的后端设计，讨论了在后端设计过程中面对的诸多问题，以及相应的解决方案。
In view of this, this article discuss the back-end design process and give some solutions to the flow which is based on digital decoder chip which is from VLSI laboratory of UESTC.
本文所开发的基于通用高性能DSP芯片的图像编解码系统具有可靠性高、速度快、体积小、功耗低和环境适应性强等优点。
The image encoder and decoder based on the general high performance DSP chip has especial advantages of high reliability, small-size, fast data processing, low power consumption and flexibility.
该系统由以单片机at89c51和双音多频mt8870解码芯片为核心的系统硬件及软件组成。
It is composed of software and hardware, with single chip AT89C51 and DTMF decoding chip MT8870 as its cores.
MPEG4编解码芯片包含了复杂的算法，利用系统设计语言建立事务级的参考模型已经非常有必要。
The MPEG4 encode and decode module include complex algorithm , so it is very necessary to build a transaction level reference module .
图像的压缩采用JPEG算法，利用JPEG编解码芯片ZR 36060完成，ZR 36060可以生成完全符合JPEG标准的数据流。
Image compression accord with JPEG standard and perform by an integrated JPEG codec ZR36060, which supports completely baseline method defined by JPEG standard.
因此，基于FPGA和一些成熟的视频编解码芯片进行系统设计具有重要的实际意义。
Therefore, it is of great significance to design a video codec system based on FPGA and some mature chip.
本文以MPEG2集成解码芯片中音频存储优化为例给出了系统集成芯片存储优化的一些方法。
In this paper, by analyzing the optimization of audio decoding in MPEG2 decoding chip, some approaches are given to optimize the memory usage of SoC.
介绍了自适应多码率语音编解码算法及其基于TMS320F 2812定点DSP芯片的实现方案。
An Implementation of the adaptive multi-rate speech codec based on the TMS320F2812 fixed-point DSP chip is presented.
设计选用PCI多媒体接口芯片SAA7146A，方便的实现了与视频编码器、视频解码器和音频编解码器的连接。
It USES the PCI interface chip SAA7146A special for media processing produced by Philips, and connects simply with video encoder, video decoder, audio encoder and decoder.
视频处理芯片是嵌入式视频系统的核心部件之一，具有视频信号采集、编码、解码、输出等功能。
Video controller chip, which is one of the important component of video embedded systems, plays an important role in video signal acquisition, decoding, encoding, output and other important functions.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。263编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 263 CODEC.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。264编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 264 CODEC.
文章介绍了基于32位ARM7芯片LPC 2292实现的软件JPEG解码算法及应用了此算法的手持JPEG图像显示器的设计。
This paper proposes a new arithmetic of JPEG decode software basing on the 32-bit ARM7 chip, LPC2292 and applying the arithmetic, a handhold JPEG image displayer is designed.
根据现有的来电显示(CID)技术规范，利用ARM7、FSK制式的来电显示解码芯片MT 88e39完成了主叫号码识别电路的设计和实现。
According to the specification of CID (calling identity delivery), the CID circuit is designed and realized by using ARM7 and FSK decoding chip MT88E39.
PM P播放器不仅需要对机体大小有所限制，更重要的是需要一种压缩效率更高、画面质量更高的视频压缩技术，以及相关编解码芯片。
PMP players need not only be limited to body size, but more importantly is the need for a more efficient compression, higher picture quality video compression technology, and related codec chips.
平板电视时代，数字电视和模拟电视的差别在于数字电视多数字电视解调芯片、MPEG - 2解码芯片，视频DAC不需要了。
In the era of flat panel TV, the difference between digital TV and analog TV is digital TV has digital TV decode chip, MPEG-2 decode chip, so video DAC is not needed.
CRT时代，数字电视与模拟电视最大的区别是数字电视多数字电视解调芯片、MPEG - 2解码芯片和视频DAC。
In the era of CRT, the largest difference between digital TV and analog TV is digital TV has digital TV decode chip, MPEG-2 decode chip and video DAC.
图像的压缩采用JPEG标准，利用JPEG编解码芯片ZR 36060完成，ZR 36060可以生成完全符合JPEG标准的数据流。
The image compression unit USES the JPEG standard and performs by an integrated JPEG codec ZR36060, which can create JPEG standard data stream.
本发明提供一种图像处理平台，其包括：一视频解码芯片，用于将输 入的模拟视频图像转化为数字视频图像；
The invention provides an image processing platform, which comprises a video decoder used for converting input simulation video images into digital video images;
然后对视频编解码芯片MB86H51的功能特性和接口进行了详细的介绍；
Secondly, it introduced the function, main specifications and interface of MB86H51 in detail.
在视频解码部分采用硬件芯片SAA7111 A对视频图像信号进行解码，提高图像显示的速度。
In the part of video decode, chip SAA7111A is adopted to decode the video image signal, enhancing the speed of image display.
然后详细介绍了该MPEG-1解码器的软硬件设计：硬件设计主要基于ESS3890解码芯片和M65827DSP 两块主要芯片；
Afterwards, it details design of both the hardware and software of MPEG-1decoder. The hardware design is mostly based on a decode chip ESS3890 and a DSP chip M65827;
提出一种新的基于嵌入式可重构系统芯片的视频解码方案，采用了软硬件协同验证的方法。
A new video decoding scheme based on embedded reconfigurable SoC is proposed. The software and hardware co-verification method is adopted in this scheme.
提出一种新的基于嵌入式可重构系统芯片的视频解码方案，采用了软硬件协同验证的方法。
A new video decoding scheme based on embedded reconfigurable SoC is proposed. The software and hardware co-verification method is adopted in this scheme.
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