因此，为了减少锁相环的个数，针对FPGA的内部结构对该方法进行了改进，提出了改进等效脉冲计数法。
So in order to reduce the number of PLL, the improved Equivalent pulse-counting method is proposed in view of the internal structure of the FPGA.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
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