在某种程度上，这些翻译者认为他们需要得到外国专家的帮助以完成这个国家级指令。
At some point, the translators decided they needed help from the foreign experts to complete the national directive.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
成功地由版本11.50 . xC 7升级到11.70 .xC1之后，您可以使用以下指令创建可信任的环境。
After converting successfully from version11.50.xC7 to 11.70.xc1, you can use the following command to create trusted context.
BCEL最大的好处是它的商业友好的Apache许可证及其丰富的JVM指令级支持。
The big advantages of BCEL are its commercial-friendly Apache licensing and its extensive JVM instruction-level support.
新增的指令是xsl:next-match，类似于 xsl:apply-imports，但是可以触发相同优先级的模板而不仅仅是较低导入优先级的模板。
The new instruction is xsl:next-match, which is similar to xsl:apply-imports but can trigger a matching template of the same precedence, not just ones of lower import precedence.
因此，在大部分体系架构上，会使用一条find - first -bit -set指令在5个32位的字(140个优先级)中哪一位的优先级最高。
Therefore, on most architectures, a find-first-bit-set instruction is used to find the highest priority bit set in one of five 32-bit words (for the 140 priorities).
在欧盟这一级别，这种做法体现在温室气体排放交易机制(“排放交易机制”)中，即2003年能源税指令以及最近刚刚修改的对超重卡车收费的Eurovignette指令。
At EU level, this approach is embodied in the greenhouse gas emissions trading scheme (ETS), the 2003 directive on energy taxation and the recently revised Eurovignette directive on truck tolls.
注销该指令曾注册到全局服务或应用级服务中的各种回调函数。
Unregister all call backs that this directive registered with global or application services.
指令调度是在保证语义正确的前提下，改变指令执行的顺序，以提高指令级并行的程度。
To change the execution order of instructions, enchant ILP furthest, will achieve higher performance on the basis of ensuring correctness.
一种基本单位或基础单位，常常指机器指令的最低一级或语言翻译的最低的单位。
A basic or fundamental unit often referring to the lowest of a machine instruction or lowest unit of language translation.
一种混合计算机级，其指令既由操作系统解释，也直接由微程序解释。
A hybrid computer level whose instructions are interpreted by both the operating system and directly by the microprogram.
通过分析影响嵌入式系统性能的主要因素，采用了基于线程概念的嵌入式系统并行设计方法，利用指令级并行来改善系统性能。
By analyzing factors impacting upon the embedded system performance, an embedded system design method based on thread ideas is used, performance is improved with instruction level parallelism.
谓词执行技术能够将多个基本块合并为一个超块，扩大指令调度范围，开发更多的指令级并行。
Several basic blocks could be merged into a hyperblock in predicated execution so that instructions could be scheduled on a larger scope and more instruction level parallelism could be extracted.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
针对笔者自主研制的LS -RISC微处理器，讨论了其指令级功耗模型的开发。
The development of instruction level power model is discussed to our self-made LS-RISC microprocessor.
在平台级优化方面，给出了操作优化、指令优化以及流水线优化等三种优化方法。
For architecture level ones, this paper introduces three kinds of optimization methods, which called operation optimization, instruction optimization and pipeline optimization.
讨论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform.
在DSP内核的设计、开发过程中，指令级模拟器可用于汇编程序仿真、调试，有利于加快芯片开发进度。
In the designing and exploitation progress of a DSP core, the instruction level simulator can be used in the emulation and debugging, and it is propitious to expedite the rate of development.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
梯度放大器是核磁共振成像(MRI)系统的核心设备之一，它根据前级控制系统传来的指令，向梯度线圈提供特定波形的电流脉冲。
The gradient amplifier is an essential equipment of Magnetic Resonance Imaging system (MRI). It supplies the gradient coils with pulse currents according to the signal from the control system.
本文针对微处理器的特点，提出了指令级全速电流测试方法。
In this paper we have proposed instruction level At-speed current testing method taking both the characteristics of microprocessor and At-speed current testing into account.
谓词支持是IA 6 4体系结构的新特征，它为发掘指令级并行提供了更多的机会，同时给编译器的设计者增加了难度。
Predication support is one of the new features of IA-64, which offers more opportunities for exploiting instruction level parallelism, however, brings some difficulties for compiler designers.
指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。
Instruction scheduling is used to exploit the instruction level parallelism (ILP) inherent in program through reordering its instructions.
为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。
In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
最后，通过ILP对该策略提出改进，以指令级并行信息指导功耗优化，在功耗优化效果损失不大的前提下，可节省多达20%的算法开销。
At last, an enhancement method for the strategy is proposed based on ILP information. The statistics shows that the cost saved can reach up to 20%.
本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。
This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors.
本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。
This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors.
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