它的第一个设计非常简单，所有指令都在一个时钟周期内完成。
Its first design was very simple and all instructions were completed in one clock cycle.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
这些系列的处理器都拥有不同的时钟频率，或者说处理器处理交给它们的指令或任务的速度。
All of those come in varying clockspeeds, or how fast a chip will perform the instructions or tasks it's given.
当它运行时，它会记录每次系统时钟中断发生时正在执行的指令的地址。
While it is running, it records the address of the instruction that is being executed every time a system-clock interrupt occurs.
POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。
The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.
除了处理器时钟速度外，另一个重要的处理器性能度量是每条指令的时钟周期(CPI)。
In addition to processor clock speed, another important processor performance metric is clock cycles per instruction (CPI).
在这个程序中，完成指令1需要花费4个时钟周期。
In this program, it takes four clock cycles for instruction 1 to finish.
不过对于现在来说，我们将简单地展示如何通过调整selb和stqd指令的顺序来节省两个时钟周期。
However, for now, I will simply show how to save two clock cycles by adjusting the order of the selb and STQD instructions. Here is the new order.
SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。
An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.
POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。
The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
暂停（Stall） ——处理器不开始执行新指令处的时钟周期。
Stall -- A clock cycle where the processor does not begin a new instruction.
指令4可以在指令3之后紧接的那个时钟周期执行，因为它不需要指令3的结果来执行。
Instruction 4 can be issued in the clock cycle immediately after instruction 3 because it does not require the result of instruction 3 to execute. You can visualize it like this.
同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。
Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.
在读操作中，如果发出了这个指令，那么两个时钟周期后，读出数据无效，数据总线进入高阻状态。
During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay.
因为不同的指令采取不同的时钟周期完成。
Coz different instructions take different clock cycles to accomplish.
文章介绍了一种采用多时钟定量系统设计八位复杂指令集微处理器的方法。
This paper introduces the multi - clocks method in 8 - bit complex instruction set MCU system - level architecture.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。
It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
处理器包含一个时钟，一条指令控制单元，一个算术和逻辑单元，并登记。
The processor contains a clock, an instruction control unit, an arithmetic and logic unit, and registers.
它用于复杂指令集计算机微处理器或者单处理机简化指令系统计算机系统的时钟分布。
It is designed to provide clock distribution for CISC microprocessors single processor RISC systems.
它用于复杂指令集计算机微处理器或者单处理机简化指令系统计算机系统的时钟分布。
It is designed to provide clock distribution for CISC microprocessors single processor RISC systems.
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