时钟抖动是输出时钟的随机变化。
输出时钟抖动定义为三种类型：周期抖动，占空比抖动和相位抖动。
Output jitter is defined in three ways: period jitter. duty-cycle jitter, and phase jitter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
利用码间串扰量的度量准则，对不同的成形滤波函数研究了插值滤波器的参数优化估计及其抗时钟抖动性能。
By using the measure criterion of intersymbol interference, the parameter optimization and robustness of timing jitter of interpolation filter for a few kinds of shaping functions has been studied.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
这是总的抖动，如果是无抖动的时钟源。
本文介绍了时钟网络中抖动、相位噪声、偏移、频率稳定度等参数的概念以及它们之间的转换关系。
The paper introduce the concepts of timing parameters, including: jitter, phase noise, skew, frequency stabilization, and the relationship between them.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
This paper adopts a strategy of fitting offset to adjust time, to conquer the impact of network delay and jitter on clock synchronization effectively.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
其也可由参考输入时钟的较大的抖动引起。
It can also be caused by excessive jitter on the REFCLK input.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
A strategy of fitting offset to adjust time is proposed to conquer the impact of network delay and jitter on clock synchronization effectively.
结果表明，采用参数佑计测量法测量时钟 抖动，不但能够准确地测出 抖动的大小，而且能够测出 抖动 的分布。
The result shows that the parameter-estimating method can measure not only the value of jitter, but also its distribution.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
The aim of this thesis is to present a new strategy of fitting offset to adjust time in order to achieve the effective synchronization between slave nod and reference node.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
The aim of this thesis is to present a new strategy of fitting offset to adjust time in order to achieve the effective synchronization between slave nod and reference node.
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