这是一个产生产生毫秒级时钟延时的程序。
This is a generated clock millisecond delay resulting procedures.
同时就设计中常遇到的三个问题：时钟延时，时钟偏移，同步器的亚稳态性加以说明且提出了解决方法。
After analyzing the Clock delay, the Clock Skew and the critical steady synchronizer which are difficult in the design, some settle methods are introduced.
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
例如，不同计算机上的时钟不同步或消息延时超过时限。
For example, clocks on different computers which are used to coordinate processes are not synchronized; when a message is delayed longer than a threshold period, etc.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
用二相时钟设计了对寄生电容低灵敏的开关电容单位延时器、负比例器和加法器。
Electric discharge characterized by a cathode fall that is small compared with that in a glow discharge.
用二相时钟设计了对寄生电容低灵敏的开关电容单位延时器、负比例器和加法器。
Electric discharge characterized by a cathode fall that is small compared with that in a glow discharge.
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