时钟偏移是同步数字集成电路设计中的一个难题。
Clock skew is in a synchronization digital integrated circuit design difficult problem.
使用那些凸包来估计所述第一和第二时钟之间的时钟偏移和歪斜。
The clock offset and the skew between said first and second clocks are estimated using those convex hulls.
典型的集群复制大概需要8秒钟左右，而我们允许1分钟的时间，以免系统时钟偏移。
A typical cluster replication is around eight seconds, and then we allow a minute more than that in case system clocks wander a bit.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
针对无线传感器网络固有的时钟偏移和时钟漂移问题，研究了不同的时间同步方法对同步精度的影响。
Concerning the clock skew and clock drift problem in wireless sensor networks, some different methods of synchronization time on synchronization accuracy were studied.
同时就设计中常遇到的三个问题：时钟延时，时钟偏移，同步器的亚稳态性加以说明且提出了解决方法。
After analyzing the Clock delay, the Clock Skew and the critical steady synchronizer which are difficult in the design, some settle methods are introduced.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
该算法利用连续两次同步过程中所记录的时间信息来估算节点时钟的偏移和频率漂移率，并进行补偿。
The clock offset and frequency drift rate for sensor nodes are estimated and then compensated by using the time-stamp recorded in two adjacent synchronizations.
本文介绍了时钟网络中抖动、相位噪声、偏移、频率稳定度等参数的概念以及它们之间的转换关系。
The paper introduce the concepts of timing parameters, including: jitter, phase noise, skew, frequency stabilization, and the relationship between them.
本文还给出了基于GPS芯片和CPLD，对系统压控晶振时钟进行校准的实现方法，有效解决了由于长时间使用，晶振自身特性变化，造成的频率偏移现象。
This paper introduces the method of clock calibration to VCXO in system, based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.
公开了用于估计计算机系统中两个时钟之间的歪斜和偏移的方法和系统。
Disclosed are a method and system for estimating the skew and offset between two clocks in a computer system.
在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。
Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
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