POWER7模型中每个插槽（常用的芯片名称）的内核数可以是4、6或8 个。
The number of cores per socket (commonly used name for a chip) for POWER7 models can be 4, 6, or 8.
而且，在这个比较慢的 366MHz芯片上可以在大约10秒内执行一百万次上下文切换（所涉及的线程数对耗时并无重大影响）。
Moreover, on this fairly slow 366 MHz chip, one million context switches can be performed in about 10 seconds (the number of threads involved is not particularly significant to the timing).
我的设计目标就是最后的芯片数一定要尽量少，更准确的说，是要让最后的电路板尽量小，因此，这些小不点的串行移位寄存器中标了。
My design goal was to have the fewest chips in the end. More correctly it was to have the smallest board space used.
确定你有一张植入了芯片的卡和四位数的密码（译者注：欧洲银行卡密码是4位），这样的安全保证已经取代了磁条在美国盛行。
Make sure you have a card with an embedded microchip and a four-digit PIN, a security feature that has replaced the magnetic strip still prevalent in the U.S.
数t510型号只有一英特尔gma高清图形芯片处理器集成到核心我。
A few T510 models only have an Intel GMA HD graphic chip integrated into the Core I processor.
单片机作为一种成熟的控制芯片，适合作为轴数不多的伺服控制系统的芯片。
The MCS takes one kind of mature control chip, suits the chip of the axis number not many servo-controls system.
集成芯片的部分。与其他部分邻接。可以指定输入、输出数目和针脚数。
Section of an integrated chip. Adjoin with other sections. Number of inputs, outputs, and pins can be specified.
介绍了对数放大器的基本概念以及利用AD 8313对数放大器集成芯片研制的实用宽带、大动态范围、高精度对数放大器模块。
This paper introduces a basic conception of logarithm amplifier and a useful logarithmic amplifier using the chip of AD8313 that has a wide bandwidth, high dynamic range and high accuracy.
随着设计规模的不断增加，芯片的平均设计门数已经超越百万级，验证已经成为设计流程中的主要瓶颈。
As the average gate count for designs now approaches or exceed on million, the verification has become the main bottleneck in design process.
我们采用的控制芯片为TI公司的MSP430，无线传输模块采用的是通用的微功率无线数传模块，串口通讯方式。
We used ti Corporation's MSP430 as control chip, while took general wireless transceiver module with UART opened as communication means.
并且完成了包括BMC、中心控制器、CODEC的无线数传芯片的ASIC实现。
It has also completed ASIC implementation of SOC that include BMC, system center controller and CODEC.
芯片规模不断增加、设计门数不断增长，验证已成为芯片开发的主要瓶颈。
With the continuing increase in chip scale and design gates, verification has become the main bottleneck in chip development.
一种程序，将外源基因芯片的数据集，基于的常见，数进行比较差异表达基因。
A program that compares heterologous microarray data sets, based on the number of common, differentially expressed genes.
其设计的优劣直接影响着FPGA实现具体设计的性能及FPGA芯片可以承载的最大系统级晶体管数。
The quality of the block's design directly effects the performance of the FPGA and the maximum system gates that FPGA included.
由于FPGA芯片的容量和管脚数的比例往往与具体的设计实体之间存在较大差异，设计的实现效率因此而受到较大影响。
But there exists the difference between the at of the capacity to the number of pin and the concrete design, which effects the implementation efficiency considerably.
由于FPGA芯片的容量和管脚数的比例往往与具体的设计实体之间存在较大差异，设计的实现效率因此而受到较大影响。
But there exists the difference between the rate of the capacity to the number of pin and the concrete design, which effects the implementation efficiency considerably.
在今天系统芯片中，片上重用的口模块数越来越多。
In the design of system-on-a-chip, the number of the intellectual property reuse-based has become more and more.
在今天系统芯片中，片上重用的口模块数越来越多。
In the design of system-on-a-chip, the number of the intellectual property reuse-based has become more and more.
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