对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
本文采用逻辑电路实现了基于采样数据的EPLL数字锁相环算法，并在FPGA电路中实现和实验验证该设计。
Through the adoption of the logic circuits, this article will successfully actualize the EPLL, which is based on the sample data, and validate this project in FPGA.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
第四章探讨了运用可编程技术设计数字锁相环和数字倍频器的相关问题，为以后电路设计拓展更多的方法。
The chapter 4 discuss some question of the circuit using programmable device like digital phase locked loop and digital frequency multiplier, it can increase the way of circuit design.
在数字延迟锁相环设计中，先整体讲述电路的整体构架的设计，然后详细阐述了基本模块的实现方法与原理。
During the design of delay - locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented.
在数字延迟锁相环设计中，先整体讲述电路的整体构架的设计，然后详细阐述了基本模块的实现方法与原理。
During the design of delay - locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented.
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