针对数字电路中多故障测试生成效率较低的问题，提出了基于神经网络的数字电路多故障测试生成算法。
A multiple faults test generation algorithm based neural networks for digital circuits is proposed considering that the test generation efficiency for multiple faults in digital circuits is low.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
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