分析了应用于时钟恢复电路中的相位插值器。
In this paper, a detailed analysis of a phase interpolator for clock recovery is presented.
介绍了一个应用在移动支付系统里的全集成载波时钟恢复电路。
This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application.
根据视频处理通道中的直流电平恢复电路的性能，部分或全部的同步脉冲不会从绿色通道中移除。
Depending on the performance characteristics of the DC restoration circuitry within the video processing channel, some or all of the sync pulse may not be removed from the green channel.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
通过电路分析，该驱动电路能够完成各个时期输出相应脉冲的要求，且能量恢复电路能够降低系统功耗。
The driving circuit can produce corresponding pulses of different period, and the energy recovery circuit can reduce the power consumption of the PDP system.
通过电路分析，该驱动电路能够完成各个时期输出相应脉冲的要求，且能量恢复电路能够降低系统功耗。
The driving circuit can produce corresponding pulses of different period, and the energy recovery circuit can reduce the power consumption of the PDP...
在上述理论分析的基础上，分别设计了三种不同结构的低功耗电源恢复电路和解调电路以及参考电压源电路等电路模块。
Thirdly, according to the design techniques mentioned above, three kinds of Low-Power rectifier, demodulator and other circuits, such as bias circuits, POR generator, etc. are put forward.
更高速率系统的研制目前也在开展中。时钟恢复电路(CRC)是光纤通信和许多类似数字通信领域中不可缺少的关键电路。
Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
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