有时，一旦把CPU使用其它外围设备所必需的总线逻辑和延迟时间考虑在内，那么快速而廉价的CPU也可能变得昂贵。
Sometimes a fast, inexpensive CPU can become expensive once bus logic and the delays necessary to make it work with other peripherals are considered.
消息的处理(或路由选择)是通过总线做到的，并且没有扰乱任何业务逻辑。
The handling (or routing) of a message is managed by the bus and does not clutter any business logic.
使用者与逻辑总线进行通信，而后者跟踪来自提供者的可用服务，并负责调用恰当的提供者。
The consumers communicate with the logical bus, which keeps track of the available services from the providers, and in turn calls the appropriate provider.
服务集成总线(SIB)是一个逻辑概念。
根据前面对集成层和服务总线的讨论，您可以看出矛盾之处；例如，业务逻辑是集成逻辑的一种形式。
Based on the above descriptions of the integration layer and the service bus, you recognize conflicts; for example, business logic is a form of integration logic.
在写数据时，主机总线适配器(HBA)根据块数据和逻辑块地址生成dif。
On a write, the DIF is generated by the host bus adapter (HBA), based on the block data and logical block address.
图3描述了一个这样的逻辑体系结构，其中的服务提供者和服务使用者通过逻辑总线进行通信。
Figure 3 depicts such a logical architecture where the service providers and service consumers communicate through a logical bus.
这个模式在一个由多个逻辑总线组成的联邦服务总线基础设施中划出了4个关注级别。
This pattern suggests four levels of interest in a federated service bus infrastructure consisting of multiple logical buses.
每一项的前三个数字分别指SCSI总线、设备标识和LUN（逻辑单元号，Logical Unit Number）。
The first three numbers for each item refer to SCSI bus, device ID, and LUN (Logical Unit Number), respectively.
Hypervisor可以确保每个逻辑分区仅能够访问分配给它的pci插槽，而不能访问其他PCI设备，即使它们处于相同的总线。
The hypervisor ensures that each logical partition can access only the PCI slots assigned to it and not other PCI devices, even if they are on the same bus.
因此，中介(和服务总线)可以包含业务逻辑，但是这些逻辑只能是非语义的。
Thus, it is fair to say that mediation (and thus the service bus) can contain business logic, but only if it is non-semantic.
每个应用绑定到它自己的逻辑总线上。
目的地是每一条发送到总线上的消息的逻辑目标。
A destination is the logical target for each message that is sent to the bus.
“企业”服务总线只在逻辑上存在，服务联合（见第 4部分）支持在整个企业内共享受治理的服务。
The "enterprise" service bus exists only logically and service federation (see part 4) supports the sharing of governed services across the enterprise.
服务公开层只能包含非语义逻辑，但是其中包括业务拥有的非语义逻辑，因此在服务总线(esb)中可以有业务逻辑。
We further showed the service exposure layer can contain only non-semantic logic, but that includes business-owned non-semantic logic, thus allowing business logic in the service bus (ESB).
单个工作线程也许就能迫使LPAR中的一个逻辑CPU达到100%的利用率，因此将总线程数量设置为CPU数量减1。
A single worker thread might be able to push one logic CPU to 100% utilization in the LPAR, so the total thread number is set to number of the CPUs minus 1.
然而，我们可以定义服务集成总线(后面简称为总线)为一个逻辑云，其可以提供消费者与提供商互连的机制。
However, here we can define the Service Integration BUS (simply BUS later) as a logical cloud, that provides the mechanisms to interconnect a consumers with a providers. This logical cloud contains.
为了排除人为干扰、提高可靠性，采集数据以可编程逻辑控制器为核心，通过现场总线和以太网的多层网络传送至数据库中。
To avoid interfering by work, data were sampled through a multi-layers network which synthesize the field-bus and Ethernet and center on programmable logic controller.
该方法将PCI总线接口和控制逻辑集成于一片FPGA中，提高了系统的集成度和可移植性。
The method which integrates PCI bus interface and control logic into a FPGA chip improves the integration density and transplantation of system.
在设计上除模拟控制及总线驱动等器件外，尽量采用FPGA来实现控制逻辑以提供应用平台的可扩展性。
Except for the analogue controlling and bus driving devices, we use FPGA to implement controlling logic in order to provide expansibility of application platform.
设计和验证超高密度FPGA的方法是采用逻辑分析仪、示波器和总线分析仪，通过测试头和连接器把信号送到仪器上。
Making use of logic analyzer, oscillograph and bus analyzer, we can design and test the superhigh density FPGA, and transmit the signal to the instrument through probe and linker.
实际运行情况表明：该系统集数字逻辑控制同复杂算法控制于一体，融会总线网络技术，较一般控制系统具备更强的适应能力和控制品质。
Practice indicate that this system have more adaptive ability and control qualities than the ordinary control system, which integrate digital logic and compound algorithm and bus network technique.
CMOS敏感器不是I2C总线电路，因此同arm连接必须有驱动电路(时序逻辑电路)。
When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.
完成了一种基于WISHBONE总线的GPIO_WB控制器的逻辑设计和物理实现。
The logic design and physical implementation of a GPIO_WB controller based on WISHBONE Bus are achieved.
PXA270处理器负责控制逻辑的运行，产生和处理CAN总线传递的数据信息。
PXA270 runs the system control logic, generate and dispose the data message transmitted by CAN bus.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
控制器的逻辑单元为多cpu网络体系，体系内各智能化功能模块通过CAN总线互联，实现模块间的数据交换和多cpu协同工作。
The logic elements in controller are multiple CPU network setup. Individual intelligent functional modules are interconnected by CAN bus for data exchanging and multiple CPU cooperating.
介绍了CAN总线适配卡的接口电路和译码逻辑。
In this paper, the hardware interface and decode logic of CAN adapter are introduced.
在令牌总线局域网络中，当逻辑环被破坏时，就要运行逻辑环维护算法。
The maintenance algorithm must be invoked, if the logical ring of the token bus LAN is broken.
在令牌总线局域网络中，当逻辑环被破坏时，就要运行逻辑环维护算法。
The maintenance algorithm must be invoked, if the logical ring of the token bus LAN is broken.
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