器件采用最小2微米设计规则，两层多晶硅结构。
This detector line array is fabricated using 2 micron design rule and a double level poly silicon structure.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
这种模块化后过滤器包括：？现代设计和外观？ 0.5微米元件？重量轻？高流量与最小压降。
This modular afterfilter includes:? Modern Design and Appearance? 0.5 Micron Element? Lightweight? High Flow Capacity with Minimal Pressure Drop.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
实现了不同粒径大小及粒径分布的微米级单分散聚合物微球制备的控制设计。
Monodisperse polymer microspheres with micron size with different size and size distribution can be designed.
巨观、微米和奈米尺度技术依赖于特定尺度的性能模型、设计方法和可用于有限范围大小的工程机械的制造过程。
Macro, micro and nano-scale technologies rely on scale-specific performance models, design methods and fabrication processes which may be used to engineer machines within a limited range of size.
本文首先分析传统设计的问题，然后针对深亚微米系统，对失配产生的问题进行比较分析，在此基础上提出改进方法和新型结构。
This thesis first analyzes basic design of sense amplifier in deep sub-micron system, compares and discusses the mismatch problem, and then the new design is presented.
模拟电路数字化虽可解决很多深亚微米工艺射频模拟集成电路设计中出现的问题，但暂时依然无法完全替代传统模拟电路器件和结构。
Though it can solve many problems during RF analog IC design in deep submicron meter technology, but it still can't i(?)place all conventional analog circuit component or structure.
深亚微米下芯片的物理设计面临很多挑战，特别是对于超大规模电路，在后端设计流程上要有新的方法。
The deep submicron technology presents lots of new challenges to the physical design of VLSI and new techniques are needed in the back-end design flow.
随着集成电路设计进入超深亚微米阶段，电路复杂度不断提高，芯片测试面临着巨大的挑战。
As the integrated circuit design has stepped into the deep ultra-submicron stage, the complexity of the circuit increases continually, chip test faces very huge challenge.
进入深亚微米工艺后，静态功耗开始和动态功耗相抗衡，已成为低功耗设计一个不可忽视的因素。
In deep sub - micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design.
成功地将共面线应用在深亚微米高速集成电路的设计中，并给出了放大器芯片和共面线的测试结果。
Finally, the coplanar stripline on-chip is successfully used in the design of the high-speed IC's, and some measured results are also given.
超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。
Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems.
针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。
A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
其提供1微米的重复精确度，这些精确的接触开关专门设计用来设定参考点，检查公差，监测，计量和校准工作。
Offering 1 micron repeat accuracy, these precision contact switches are designed for setting reference points, checking tolerances, monitoring, gauging and calibrating tasks.
对标准GDSII(图形设计系统II)流文件，米制设计的分辨率为0.001微米。
For a standard GDSII (Graphic design System II) stream file, the resolution is 0.001 micron for metric designs.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
超深亚微米ic设计中互连线的串扰情况与详细布线方案和信号波形密切相关。
In IC design under VDSM technology, the crosstalk situation of interconnecting is related nearly with the scheme of detailed routing and the waveforms of signals.
本文介绍了当今RF设计的主流工艺，并分别对基于硅的深亚微米cmos工艺在RF设计中的可行性和困难进行了研究，评述了其中存在的问题。
This paper presented the various technologies in RF design and explored the feasibility and difficulties of deep sub micron CMOS RF design. And problems associated are also discussed.
在妥善设计和安装，FOGCO系统产生的水滴10微米的雾高浓度。
When properly designed and installed, the FOGCO System produces a high concentration of 10 micron fog droplets.
微处理器采用0.18微米工艺全定制设计，其电路形式异常烦杂。
X microprocessor is a full-custom circuit designed under 0.18um process, it contains a lot of complicated design types.
光刻校正技术已成为超深亚微米下集成电路设计和制造中关键的技术。
The optical lithography correction techniques become key technologies in the IC designing and manufacturing of VDSM.
独特的流体运动高设计使物料变成了超细的微米级粉末。它对节约原材料，降低成本、提高产品档次有着重大的意义。
By the special fluid movement design, the raw materials become superfine micron - size powders, which is significant to save the raw materials, reduce the cost and raise the grade of products.
熟悉深亚微米工艺设计规则。
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
在设计和加工微小型零件时，由于现有公差数值表缺少对微米和中间尺度的描述，因而使得批量生产和控制表面质量、加工精度极为不便。
The existing tolerance value table is imperfect, resulting in a range of issues such as batch production, surface quality and machining accuracy in designing and processing microminiature parts.
研究微米级磁致伸缩微位移机构的控制技术，设计并实现了一个二维平面行走伸缩机构的PWM脉冲驱动控制系统。
The control mechanism of magnetostrictive microdisplacement actuator is investigated. A PWMbased system to control a microdisplacement actuator of two dimensions is designed and implemented.
该文利用简单廉价的机电结构实现了微米级的机电一体化系统的设计，该系统可用于在约束条件下测量混凝土的内应力。
A micron electro-mechanical system was designed by using simple and cheap structure. The system can be used to measure the internal stress of concrete on the condition of being constrained.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
应用推荐