• 相位频率检测器比较基准时钟信号反馈时钟信号从而一个更多输出信号中生成脉冲

    A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.

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  • 基准反馈时钟信号相位频率同时,PLL处于锁定模式且PFD输出信号生成脉冲

    When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.

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  • 环路反馈结构,包括插值器、时钟误差检测环路滤波器三个部分。

    The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

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  • 相位抖动反馈时钟参考时钟之间上升沿差异多次随机采样平均偏移之间差。

    Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.

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  • 相位抖动反馈时钟参考时钟之间上升沿差异多次随机采样平均偏移之间差。

    Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.

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