相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。
Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
这种方法比反馈环法定时精度高，定时误差捕获快，并且不需要时钟源，不占用片内硬件资源，适合于全软件化设计要求。
Contrasted with the feedback loop this method is more accurate, the timing error is caught faster, the time resource is not necessary and it does not occupy resources of the hardware in DSP.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
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