静态时序分析(英语:Static Timing Analysis, STA),或称静态时序验证,是电子工程中,对数字电路的时序进行计算、预计的工作流程,该流程不需要通过输入激励的方式进行仿真。
静态时序分析的实现。
静态时序分析是一种彻底的分析、调试、验证设计的方法。
Static timing analysis is an exhaustive method of analyzing, debugging and validating design performance.
因为运行时候可能长达良多个小时,静态时序分析已经成为良多ic设计团队的瓶颈。
Because run time may is as long as, make many hours, static sequential analysis has become a lot of IC to design the bottleneck of the group.
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