介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
同时对机构进行了静态和动态特性理论分析，提出了机构静态和动态计算解析式，并用有限元方法对机构动态和静态特性进行了验证。
Theoretical analysis is done on the static and dynamic characteristics of the structure, differential equations are presented, and it is also verified by the finite element method.
静态时序分析是一种彻底的分析、调试、验证设计的方法。
Static timing analysis is an exhaustive method of analyzing, debugging and validating design performance.
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