因此，为了减少锁相环的个数，针对FPGA的内部结构对该方法进行了改进，提出了改进等效脉冲计数法。

So in order to reduce the number of PLL, the improved Equivalent pulse-counting method is proposed in view of the internal structure of the FPGA.

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针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。

Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.

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