缓冲存储器周期的一部分,在这期间,逻辑与算术运算器必须中止操作或不能与存储器传输信息。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
计算机包括五个基本部分:输入设备、存储器、算术逻辑运算器、控制器和输出设备。
The computers contains 5 basic sections:input , memory, arithmetic and logic, control, and output.
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