低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
他由一个8位6502 CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
应用推荐