控制程序采用模块化的设计方法,用VHDL实现电路行为的描述,采用状态机控制整个流程,实现对各路控制信号的同步。
The control programme describes the circuit behavior in VHDL by employing the modularized design method and USES state machines to synchronize the control signals.
首先介绍了子系统的结构和工作流程,并根据功能将子系统划分为数据管理、配置管理和通话行为分析3大模块。
Firstly it introduced the architecture and workflow of subsystem, then divided subsystem into 3 modules, such as data manage module, configuration manage module and call record analysis module.
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