首批芯片的数据率为2.5吉比特每秒；该架构支持10吉比特每秒的速率。
The data rate of this initial chip is 2.5 gigabits per second; the architecture supports a rate of 10 gigabits per second.
目标应用场合包括：每秒100吉比特的长距离极化多路（pol-mux）（差分）正交相移键控（QPSK），40吉比特每秒的长距离（差分）正交相移键控和40G/100G并行网络。
The target applications include 100-gigabit-per-second long-haul pol-mux (D)QPSK, 40-gigabit-per-second long-haul (D)QPSK, and 40G/100G parallel networking.
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