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使用的标准单元类型具有较大程度的相似性，有利于基于标准单元布局布线软件进一步减少芯片面积。
Cells used in the circuit have much similarity, which helps further reduction of chip areas in the layout procedure based on standard cells.
下面的图展示了LEF标准单元和形状类似的布局数据。
The following figure shows a LEF standard cell with shapes similar to layout data.
对MCNC 标准单元测试电路中组合和时序电路的实验结果显示， 电路经过时延驱动优化布局后的最大路径时延最多减少了31%。
MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.
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