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条件赋值

网络释义

  WHEN-ELSE

1、VHDL中的并行赋值对应于VERILOG中的连续赋值,但VHDL条件赋值WHEN-ELSE)和选择赋值(WTH-SELECT)要强于VERILOG中的“?:”。

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短语

条件信号赋值 conditional signal assignment

条件信号赋值语句 Conditional Signal Assignment Statement ; SELECTED SIGNAL ASSIGNMENTS

在条件表达式里赋值 Assignment in Conditional Expression

有道翻译

条件赋值

Conditional assignment

以上为机器翻译结果,长、整句建议使用 人工翻译

双语例句

  • 使用等于号来向变量而不是像一个条件中那样使用双等于号 (==) 来比较

    Use the single equal sign to assign a value to a variable, unlike the double equal sign (==), as in the previous condition, which compare the values.

    youdao

  • 避免ifwhile语句条件部分进行赋值

    Avoid doing assignments in the condition part of if and while statements.

    youdao

  • 用户来说,最棒他们不再局限简单;用Lua表达配置文件可以注释条件

    What makes this excellent for users is that they are no longer restricted to simple assignments of values; configuration files expressed as Lua can have comments, conditionals, and more.

    youdao

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