时钟误差是网络测量中最主要的直接误差来源。
Clock error is the main and direct source of errors in network measurement.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
通过研究普通时钟行为特点，分析时钟误差产生的原因和规律，提出了一种离线时钟同步算法，并对其性能进行了分析。
A kind of offline clock synchronization algorithm is promoted based on the character of clock behavior and the cause and pattern of inaccuracy, with performance analysis provided.
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