该比较器包含一级预放大器、动态锁存器及时钟控制反相器。

The comparator includes a preamplifier, a dynamic latch and a clocked inverter.

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在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。

For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.

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在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。

The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.

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