ISP的应用减小了编码器体积，提高了稳定性，还使一种结构、多种输出组合成为可能，并可方便地将并行输出信号转换为串行信号。
The application of ISP device reduces encoder volume and improves its stability. It makes the combination of one configuration with multi-output possible, and t…
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出数据通过串行或并行端口从输出寄存器中存取，这可实现与现代微控制器和数字信号处理器的轻松、高速接口。
The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors.
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