因此在集成电路设计中，互连工艺波动对集成电路性能的影响变得至关重要。
So the impact of process fluctuations on performance has become extremely critical in IC design.
随着集成电路特征尺寸的不断减小，互连线的串扰噪声对工艺波动的灵敏度也在相应增加。
As the IC feature size continues to decrease, interconnect cross-talk noise with the process fluctuation is also a corresponding increase in sensitivity.
基于概率解释算法的原理，提出了一种考虑工艺波动的RLC互连延时统计模型，该模型使用了对数正态分布函数。
Based on the theory of the probability interpretation algorithm, a statistical model of RLC interconnect delay in the presence of process variations was put forward.
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