这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
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