处理器L2缓存 Processor L2 Cache
共处理机缓存器 coprocessor register
数字共处理机缓存器 numeric coprocessor registers
多功能移自处理缓存器 multifunction processing register MFPR
浮点处理机缓存器 floating point processor register
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
正面评价：不必清除XSL处理器缓存。与样式表关联的XSL处理器可以一直使用到样式表改变为止，但样式表的更改一般不会在运行时发生。
A positive note: the XSL processor cache does not need to be flushed; XSL processors with associated style sheets can be used until the style sheets change, which typically does not occur at run time.
对象最终存储在内存中，但编译器、运行库、处理器或缓存可以有特权定时地在变量的指定内存位置存入或取出变量值。
Objects are ultimately stored in memory, but the compiler, runtime, processor, or cache may take some liberties with the timing of moving values to or from a variable's assigned memory location.
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