全加器英语名称为full-adder，是用门电路实现两个二进制数相加并求出和的组合线路，称为一位全加器。一位全加器可以处理低位进位，并输出本位加法进位。多个一位全加器进行级联可以得到多位全加器。常用二进制四位全加器74LS283。
... three-input adder 全加器 three-input multiplexer 三输入多路转换器 Three-line input terminal 三线输入端子 ...
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... complete abstraction 纯抽象 complete action 法律上完成生效的行为 complete adder 全加器 ...
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Functional testing of a FPGA is investigated by implementing a full adder in it.
以一位全加器为例，研究了器件的功能测试方法。
参考来源 - 基于SRAM技术的现场可编程门阵列器件设计技术研究The analog part includes one-bit DAC and analog low-pass filter. By analyzing every part of∑D/A converter, it is demonstrated that power consumption is mainly produced by the full-adder and register of digital part.
通过对各个部分的功耗分析表明,电路功耗主要由数字部分的全加器和寄存器产生。
参考来源 - 低功耗∑ D/A转换器设计A complete test set of full adder which is the basic component of floating-point-adder will be generated . The reorder for the test patterns of full adder can help to acquire the hard to detect patterns for floating–point-adder.
首先针对难测故障,利用故障激活条件,蕴含条件,线确认条件,生成浮点加法器基本组成部件全加器的完全测试集,对全加器测试图形进行排序获得浮点加法器的难测故障测试图形。
参考来源 - FPU中浮点加法器的设计及其内建自测试的研究·2,447,543篇论文数据，部分数据来源于NoteExpress
所提出的方法已用一位全加器的设计实例予以演示。
The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.
提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器。
In this paper, we present a polarization-encoded optical full adder by using an inverse vector realized by transmissive feedback.
用八位全加器的工作，说明了流水线技术在PLD设计中的应用。
We gave logic device of the 8bit full-adder of flow work. Introduce apple of the flow work on PLD design.
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