该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟,用于高速高精度背板测试平台。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
本文给出了一种采用自偏置技术的低抖动延迟锁相环,可应用于高频时钟产生电路。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
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