... 时钟逻辑，重复脉冲逻辑，定时逻辑 clocked logic 计时，产生时钟信号，产生时钟脉冲 clocking 计时误差，时钟误差 clocking error ...
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异步中断是由其他硬件设备产生的，可以在CPU时钟信号的任意时刻到来。
Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals.
文章介绍利用多时钟产生存储器接口控制信号的方法，为建立软核仿真平台提供了一个新的途径。
This paper presents a way to generate control signals of the interface of memory using many clocks, and offers a new way for setting up the soft-core simulation platform.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
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