对互连寄生电容提取的研究背景进行了简要的介绍。

In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.

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在大量仿真数据以及当前集成电路设计工艺的基础上，提出了一种简单互连线负载的有效电容计算模型。

A simple and efficient model was presented for computing the effective capacitance of interconnect load based on simulation and integrated circuit process.

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基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。

An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.

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