Wishbone bus architecture Wishbone总线结构
WishBone bus protocol WishBone总线协议
Wishbone Bus Interface WISHBONE总线接口
The WISHBONE bus is suitable for system communication on chip and configurable.
内部总线采用适合片上系统通信，高可配置性的WISHBONE总线。
The logic design and physical implementation of a GPIO_WB controller based on WISHBONE Bus are achieved.
完成了一种基于WISHBONE总线的GPIO_WB控制器的逻辑设计和物理实现。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
应用推荐