Static timing analysis is an exhaustive method of analyzing, debugging and validating design performance.

静态时序分析是一种彻底的分析、调试、验证设计的方法。

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In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.

文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。

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In the nuclear signal time analysis, it is a common method of using the leading edge timing error analysis.

在核信号时间分析中，前沿定时误差分析是常用的方法。

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