以下流程可分成三大部分: • 对源文件进行综合及测试预备编译(TEST READY COMPILE); • 建立扫描通路(SCAN CHAINS); • 产生测试矢量集。
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At sometime, just one scan chain or some of the scan chains are active. Average power is reduced.
在某些时刻,仅有一个或者一部分扫描链是活跃的,从而电路的平均功耗和总功耗降低。
Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT).
通过产生多个扫描链并将其施加于被测器件(DUT)的多个管脚,可以进一步减少处理时间。
In detail, the inventive methodology is based on the use of scan chains being implemented in the integrated circuit for production testing purposes.
具体地,本发明的方法基于实现在集成电路中用于产品测试目的的扫描链的使用。
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