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sample and hold circuit

  • 取样维持电路

网络释义

  取样保持电路

... sampling 5sB:mpliN v. 取样 sampling and hold circuit 取样保持电路 sampling bench 取样台 ...

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双语例句

  • Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.

    采样速度保持精度采样保持电路设计制作者最为关注项指标

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  • The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.

    采样保持电路设计采用了电容极板采样技术不仅有效地避免电荷注入效应引起采样信号失真而且消除了时钟馈通效应的不良影响。

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  • The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use.

    AD 9446款16芯片采样模数转换器(adc),内置片内采样保持电路,专门针对高性能尺寸易用性进行了优化

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