Sample And Hold Circuit 取样维持电路 ; 采样保持电路 ; 采样和保持电路 ; 抽样保持电路
pulse sample-and-hold circuit 脉冲取样保持电路 ; 脉冲抽样保持电路
The simulation shows that the sample-and-hold circuit has 10bit resolution, 80dB SFDR and 30.1mW power consumption for the frequency of 100MSPS.
结果证明:采保电路达到了10位精度、100Mhz 采样频率,消耗功率30.1mW 的技术指标。
参考来源 - 10bits 100MSPS Pipelined ADC的采保和时钟电路研究与设计·2,447,543篇论文数据，部分数据来源于NoteExpress
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。
Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。
Sample the negative voltage on the diode series with IGBT by Peak hold switch circuit, and cut-in A/D module in the DSP, compared with setting value.
通过电压峰值采样保持电路对IGBT串联二极管反压值进行采样，后经DSP A/D转换模块与反压设定值进行比较。
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