In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
应用推荐