Higher performance of the on-chip interconnection is needed because of the improvement of the system-on-chip integration and application requirements.
应用需求的增长和系统芯片集成度的不断提高，对系统芯片片上互连结构提出了更高的要求。
Such run time adaptive network on chip will adapt the underlying interconnection infrastructure on demand in response to changing communication requirements imposed by an application and context.
通过这些片上自适应网络元件与体系，将来物联网中的基本通信跟交互设施将可能根据环境跟利用中始终变更的通信须要自主的进行恰当的响应。
The implementation based on a FPGA chip has verified the feasibility and the correctness of the interconnection network interface card built on the virtual DDR memory, and verified the memory itself.
基于FPGA的实现验证了虚拟DDR存储器及建立其上的网络适配器的可行性和正确性。
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