A solution for property verification of synchronous VHDL design is introduced, and VERIS an efficient symbolic model checker is implemented.
介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案——一个有效的符号模型判别器veris。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
By the verification of error analysis, the accuracy and reliability of the model accord with the designing demands, and can be used by the production and design units.
经过误差分析验证，模型的精度、可靠度均满足设计要求，可供生产设计单位使用。
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