Then it mainly discusses the hardware design of the key unit in LDPC decoder-check functional unit.

紧接着讨论了LDPC译码器中的核心运算单元一校验功能单元的硬件设计。

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For the detected error words by the LDPC decoder, the characteristics of code bits reliability information is investigated.

分析了低密度校验(LDPC)码译码所产生的错误码字中码位的译码输出量可靠度信息的统计特性。

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With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.

随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。

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