Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
The concept of IP soft core is introduced.
简单介绍了IP软核的概念。
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