gate delay time 门信号延迟时间
trigger gate delay 触发门脉冲延迟
GDT Gate Delay Time 门延迟时间
trigger-gate delay 选择脉冲延迟
delay gate generator 延迟选通脉冲发生器
gate delay fault 门时滞故障
logic gate delay 逻辑门延时
gate delay faults 门时滞故障
gate-delay interval 门限滞后时间
So, the test patterns generated according to fixed gate delay assignments may not activate faults, or weaken the difference between the average IDDT value of a fault-free circuit and a faulty circuit in real test applications.
因此，在实际测试应用中，根据固定门延时所产生的测试向量可能无法激活故障，也可能减小故障电路和无故障电路平均瞬态电流的差别而达不到可测的要求。
参考来源 - 基于非确定门延时的瞬态电流测试生成算法研究及BIST测试产生器设计The simulation is divided into two parts: One is the logic function simulation, the other is simulation including information of the netlist and gate delay. Within the whole design, we split CAN controller into three modules.
仿真波形分析包括:第一,证明设计出的模块逻辑功能的正确性;第二,通过Quartus软件的自动综合,生成网表之后,仿真包含门延迟,所以可以证明设计的实际性。
参考来源 - 基于Verilog HDL设计CAN控制器·2,447,543篇论文数据，部分数据来源于NoteExpress
绝不要依靠门延迟。
Then, CL-ACL structure is improved, simulation and verification under real gate delay is done.
改进了互补逻辑—交替互补逻辑(CL - ACL)结构，并做了考虑门级延迟的模拟验证。
Real time graphic display of probe position, beam surface position, gate delay and gate width during scanning.
实时显示探针位置所对应的图形，播送表面位置，门控和门控宽度。
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