Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed.
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究，提出一种带复位功能的低功耗十进制计数器设计方案。
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