Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
静态时序分析由于速度快和容量大而广泛应用于时序验证,而门延时的计算则是静态时序分析中的关键部分。
In the project of HDTV channel receiving ASIC, DFT techniques based on scan-chains, STA (Static Timing Analysis) and formal verification has been adopted.
数字高清晰度电视信道接收芯片实现中使用了基于扫描链的可测试设计和静态验证技术。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证,并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
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